module ALU_7bit_unsigned(Abus, Bbus, resultbus, zerobit, overflowbit, ALUop0,ALUop1,ALUop2);

input [6:0]Abus, Bbus;
output [6:0]resultbus;
input ALUop0,ALUop1,ALUop2;
output zerobit, overflowbit;

wire [7:0]carry;

assign carry[0]=ALUop2;

ALU_1bit one00(Abus[0],Bbus[0],carry[0],carry[1],resultbus[0],ALUop0,ALUop1,ALUop2);
ALU_1bit one01(Abus[1],Bbus[1],carry[1],carry[2],resultbus[1],ALUop0,ALUop1,ALUop2);
ALU_1bit one02(Abus[2],Bbus[2],carry[2],carry[3],resultbus[2],ALUop0,ALUop1,ALUop2);
ALU_1bit one03(Abus[3],Bbus[3],carry[3],carry[4],resultbus[3],ALUop0,ALUop1,ALUop2);
ALU_1bit one04(Abus[4],Bbus[4],carry[4],carry[5],resultbus[4],ALUop0,ALUop1,ALUop2);
ALU_1bit one05(Abus[5],Bbus[5],carry[5],carry[6],resultbus[5],ALUop0,ALUop1,ALUop2);
ALU_1bit one06(Abus[6],Bbus[6],carry[6],carry[7],resultbus[6],ALUop0,ALUop1,ALUop2);

nor notand00 (zerobit,resultbus[0],resultbus[1],resultbus[2],resultbus[3],resultbus[4],resultbus[5],resultbus[6]);
assign overflowbit=carry[7];

endmodule
